More particularly, the invention is directed to the communication of data between an on-chip bus and a so-called network-on-chip system. As a matter of fact, researchers have recently proposed the network-on-chip concept (NoC) to overcome the limitations relating to the huge efforts necessary to adequately design on-chip communication systems.
NoC aims at providing scalable and flexible communication architectures with suitable performance. NoCs are based on a packet switched communication concept and mainly include three NoCs modules, namely a router, a network interface (NI), and a link.
Concerning the data format, data packets within a NoC generally include a header and a payload. The header is responsible for carrying all the information required for performing communication, whereas the payload contains the actual information to be transmitted.
Conversely, data packets transmitted over an on-chip bus are based on specific transaction protocols. For example, the so-called “ST bus,” developed by the Applicant, is based on a “ST bus protocol type 3” using a separate request channel and a response channel to provide communication between an initiator module and a target module.
Conversion of data may be carried out to provide communication between such separate interconnection systems. In addition, when clocks differ, synchronization is to be carried out to allow communication between such interconnection systems.
Usually, network interfaces are, in particular, provided to connect communicating blocks of an integrated circuit to the network and between the on-chip bus and the router of the NoC in order to convert data from one packet format to another.
In one approach according to the prior art, data communication between two interconnection systems is based on the use of a processing unit associated with a direct memory access (DMA), the processing unit being used as a master unit to send a load request to a source target to retrieve data from a first address. The processing unit also sends a store request to a destination target to store the retrieved data at a destination address, previously stored in the DMA engine.
However, such a communication system is limited due to the fact that it is, in general, slow and thus very time consuming. In addition, the processing unit is unavailable during the whole data transfer process. As a matter of fact, a standard DMA engine uses more than one (usually 8) channels. Each channel used for a different DMA transfer and a particular “channel x” is unavailable during a certain DMA transfer related to itself.